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AM29LV640D/Am29LV641D
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO Control
DISTINCTIVE CHARACTERISTICS
s Single power supply operation -- 3.0 to 3.6 volt read, erase, and program operations s VersatileIO control -- Device generates output voltages and tolerates data input voltages on the DQ input/ouputs as determined by the voltage on VIO s High performance -- Access times as fast as 90 ns s Manufactured on 0.23 m process technology s CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices s SecSi (Secured Silicon) Sector region -- 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number -- May be programmed and locked at the factory or by the customer -- Accessible through a command sequence s Ultra low power consumption (typical values at 3.0 V, 5 MHz) -- 9 mA typical active read current -- 26 mA typical erase/program current -- 200 nA typical standby mode current s Flexible sector architecture -- One hundred twenty-eight 32 Kword sectors s Sector Protection -- A hardware method to lock a sector to prevent program or erase operations within that sector -- Sectors can be locked in-system or via programming equipment -- Temporary Sector Unprotect feature allows code changes in previously locked sectors s Embedded Algorithms -- Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors -- Embedded Program algorithm automatically writes and verifies data at specified addresses s Compatibility with JEDEC standards -- Pinout and software compatible with single-power supply Flash -- Superior inadvertent write protection s Minimum 1 million erase cycle guarantee per sector s Package options -- 48-pin TSOP (Am29LV641DH/DL only) -- 56-pin SSOP (AM29LV640DH/DL only) -- 63-ball Fine-Pitch BGA (AM29LV640DU only) -- 64-ball Fortified BGA (AM29LV640DU only) s Erase Suspend/Erase Resume -- Suspends an erase operation to read data from, or program data to, a sect27 -- or that is not being erased, then resumes the erase operation s Data# Polling and toggle bits -- Provides a software method of detecting program or erase operation completion s Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences s Ready/Busy# pin (RY/BY#) (AM29LV640DU in FBGA package only) -- Provides a hardware method of detecting program or erase cycle completion s Hardware reset pin (RESET#) -- Hardware method to reset the device for reading array data s WP# pin (Am29LV641DH/DL in TSOP, AM29LV640DH/DL in SSOP only) -- At VIL, protects the first or last 32 Kword sector, regardless of sector protect/unprotect status -- At VIH, allows removal of sector protection -- An internal pull up to VCC is provided s ACC pin -- Accelerates programming time for higher throughput during system production s Program and Erase Performance (VHH not applied to the ACC input pin) -- Word program time: 11 s typical -- Sector erase time: 0.9 s typical for each 32 Kword sector
Publication# 22366 Rev: B Amendment/+8 Issue Date: September 20, 2002
Refer to AMD's Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The AM29LV640DU/Am29LV641DU is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory devices organized as 4,194,304 words. Data appears on DQ0-DQ15. The device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed in standard EPROM programmers. Access times of 90 and 120 ns are available for applications where VIO VCC. Access times of 100 and 120 ns are available for applications where VIO < VCC. The device is offered in 48-pin TSOP, 56-pin SSOP, 63-ball Fine-Pitch BGA and 64-ball Fortified BGA packages. To eliminate bus contention each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on V IO . V IO is available in two configurations (1.8-2.9 V and 3.0-5.0 V) for operation in various system environments. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The device offers a standby mode as a power-saving feature. Once the system places the device into the standby mode power consumption is greatly reduced. The SecSi (Secured Silicon) Sector provides an minimum 128-word area for code or data that can be permanently protected. Once this sector is protected, no further programming or erasing within the sector can occur. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP# pin. The protected sector will still be protected even during accelerated programming. The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to VHH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase factory throughput during system production, but may also be used in the field if desired. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
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TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Special Handling Instructions for FBGA/fBGA Packages ......... 8 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11
Table 1. Device Bus Operations .....................................................11
RY/BY#: Ready/Busy# ............................................................ 31 DQ6: Toggle Bit I .................................................................... 31
Figure 6. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ................................................................... 32 Reading Toggle Bits DQ6/DQ2 ............................................... 32 DQ5: Exceeded Timing Limits ................................................ 32 DQ3: Sector Erase Timer ....................................................... 32
Table 11. Write Operation Status ................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 7. Maximum Negative Overshoot Waveform ..................... 34 Figure 8. Maximum Positive Overshoot Waveform....................... 34
VersatileIO (VIO) Control ..................................................... 11 Requirements for Reading Array Data ................................... 11 Writing Commands/Command Sequences ............................ 12
Accelerated Program Operation ......................................................12 Autoselect Functions .......................................................................12
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ........................................... 36 Figure 10. Typical ICC1 vs. Frequency ............................................ 36
Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 13
Table 2. Sector Address Table ........................................................13
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup.................................................................... 37 Table 12. Test Specifications ......................................................... 37
Autoselect Mode ..................................................................... 17
Table 3. Autoselect Codes, (High Voltage Method) .......................17
Key to Switching Waveforms. . . . . . . . . . . . . . . . 37
Figure 12. Input Waveforms and Measurement Levels...................................................................... 37
Sector Group Protection and Unprotection ............................. 18
Table 4. Sector Group Protection/Unprotection Address Table .....18
Write Protect (WP#) ................................................................ 19 Temporary Sector Group Unprotect ....................................... 19
Figure 1. Temporary Sector Group Unprotect Operation................ 19 Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 20
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 Read-Only Operations ........................................................... 38
Figure 13. Read Operation Timings ............................................... 38
Hardware Reset (RESET#) .................................................... 39
Figure 14. Reset Timings ............................................................... 39
SecSi (Secured Silicon) Sector Flash Memory Region .......... 21
Table 5. SecSi Sector Contents ......................................................21
Erase and Program Operations .............................................. 40
Figure 15. Program Operation Timings.......................................... Figure 16. Accelerated Program Timing Diagram.......................... Figure 17. Chip/Sector Erase Operation Timings .......................... Figure 18. Data# Polling Timings (During Embedded Algorithms)...................................................... Figure 19. Toggle Bit Timings (During Embedded Algorithms)...................................................... Figure 20. DQ2 vs. DQ6................................................................. 41 41 42 43 44 44
Hardware Data Protection ...................................................... 21
Low VCC Write Inhibit .....................................................................21 Write Pulse "Glitch" Protection ........................................................22 Logical Inhibit ..................................................................................22 Power-Up Write Inhibit ....................................................................22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 6. CFI Query Identification String .......................................... 22 System Interface String................................................................... 23 Table 8. Device Geometry Definition .............................................. 23 Table 9. Primary Vendor-Specific Extended Query ........................ 24
Temporary Sector Unprotect .................................................. 45
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 45 Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 46
Command Definitions . . . . . . . . . . . . . . . . . . . . . 24 Reading Array Data ................................................................ 24 Reset Command ..................................................................... 25 Autoselect Command Sequence ............................................ 25 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 25 Word Program Command Sequence ..................................... 25
Unlock Bypass Command Sequence ..............................................26 Figure 3. Program Operation .......................................................... 26
Alternate CE# Controlled Erase and Program Operations ..... 47
Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings .............................................. 48
Chip Erase Command Sequence ........................................... 26 Sector Erase Command Sequence ........................................ 27 Erase Suspend/Erase Resume Commands ........................... 27
Figure 4. Erase Operation............................................................... 28
Command Definitions ............................................................. 29
Command Definitions...................................................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 30 DQ7: Data# Polling ................................................................. 30
Figure 5. Data# Polling Algorithm ................................................... 30
Erase And Programming Performance . . . . . . . 49 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 49 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 50 SSO056--56-Pin Shrink Small Outline Package (SSOP) ...... 50 FBE063--63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package ................................................. 51 LAA064--64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm package ................................................. 52 TS 048--48-Pin Standard TSOP ............................................ 53 TSR048--48-Pin Reverse TSOP ........................................... 54 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
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AM29LV640D/Am29LV641D
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PRODUCT SELECTOR GUIDE
Part Number Speed Option Max Access Time (ns) CE# Access Time (ns) OE# Access Time (ns) Note: See "AC Characteristics" for full specifications. VCC = 3.0-3.6 V, VIO = 3.0-5.0 V VCC = 3.0-3.6 V, VIO = 1.8-2.9 V 90 90 35 90R 101R 100 100 35 AM29LV640D/Am29LV641D 120R 121R 120 120 50
BLOCK DIAGRAM
RY/BY# (Note 1) VCC VSS RESET# Erase Voltage Generator VIO Input/Output Buffers Sector Switches DQ0-DQ15
WE# WP# (Note 2) ACC
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Timer Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A21
Notes: 1. RY/BY# is only available in the FBGA package. 2. WP# is only available in the TSOP and SSOP packages.
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CONNECTION DIAGRAMS
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RESET# ACC WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin Standard TSOP (Am29LV641DH/DL only)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 VIO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
A16 VIO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-Pin Reverse TSOP (Am29LV641DH/DL only)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RESET# ACC WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1
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CONNECTION DIAGRAMS
ACC WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC NC NC A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56-Pin SSOP (AM29LV640DH/DL only)
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
RESET# WE# A20 A21 A8 A9 A10 A11 A12 A13 A14 A15 NC NC NC NC A16 VIO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
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AM29LV640D/Am29LV641D
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CONNECTION DIAGRAM
63-Ball Fine-Pitch BGA (FBGA) Top View, Balls Facing Down (AM29LV640DU only)
A8 NC A7 NC
B8 NC B7 NC C7 A13 C6 A9 C5 WE# C4 RY/BY# C3 A7 D7 A12 D6 A8 D5 RESET# D4 ACC D3 A17 D2 A4 E7 A14 E6 A10 E5 A21 E4 A18 E3 A6 E2 A2 F7 A15 F6 A11 F5 A19 F4 A20 F3 A5 F2 A1 G7 A16 G6 DQ7 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 H7 VIO H6 DQ14 H5 DQ12 H4 DQ10 H3 DQ8 H2 CE# J7 DQ15 J6 DQ13 J5 VCC J4 DQ11 J3 DQ9 J2 OE# K7 VSS K6 DQ6 K5 DQ4 K4 DQ3 K3 DQ1 K2 VSS
L8 NC* L7 NC*
M8 NC* M7 NC*
A2 NC* A1 NC* B1
C2 A3
L2 NC* L1
M2 NC* M1 NC*
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
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CONNECTION DIAGRAMS
64-Ball Fortified BGA (FBGA) Top View, Balls Facing Down (AM29LV640DU only)
A8 RFU A7 A13 A6 A9 A5 WE# A4 RY/BY# A3 A7 A2 A3 A1 RFU
B8 RFU B7 A12 B6 A8 B5 RESET# B4 ACC B3 A17 B2 A4 B1 RFU
C8 RFU C7 A14 C6 A10 C5 A21 C4 A18 C3 A6 C2 A2 C1 RFU
D8 VIO D7 A15 D6 A11 D5 A19 D4 A20 D3 A5 D2 A1 D1 RFU
E8 VSS E7 A16 E6 DQ7 E5 DQ5 E4 DQ2 E3 DQ0 E2 A0 E1 RFU
F8 RFU F7 NC F6 DQ14 F5 DQ12 F4 DQ10 F3 DQ8 F2 CE# F1 VIO
G8 RFU G7 DQ15 G6 DQ13 G5 VCC G4 DQ11 G3 DQ9 G2 OE# G1 RFU
H8 RFU H7 VSS H6 DQ6 H5 DQ4 H4 DQ3 H3 DQ1 H2 VSS H1 RFU
Special Handling Instructions for FBGA/fBGA Packages
Special handling is required for Flash Memory products in BGA packages.
Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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PIN DESCRIPTION
A0-A21 = 22 Addresses inputs DQ0-DQ15 = 16 Data inputs/outputs CE# OE# WE# WP# ACC RESET# RY/BY# VCC = Chip Enable input = Output Enable input = Write Enable input
LOGIC SYMBOL
22 A0-A21 CE# OE# WE# DQ0-DQ15 16
= Hardware Write Protect input (N/A on FBGA) = Acceleration Input = Hardware Reset Pin input = Ready/Busy output (FBGA only) = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = Output Buffer power = Device Ground = Pin Not Connected Internally
WP# ACC RESET# VIO RY/BY#
Note: WP# is not available on the FBGA package. RY/BY# is not available on the TSOP and SSOP packages.
VIO VSS NC
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ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM29LV640D Am29LV641D H 90R E I N
OPTIONAL PROCESSING Blank= Standard Processing N = 32-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) Z = 56-Pin Shrink Small Outline Package (SSO056) PC = 64-Ball Fortified Ball Grid Array (FBGA), 1.0 mm pitch, 13 x 11 mm package (LAA064) WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 11 x 12 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected U = Uniform sector device (WP# not available) DEVICE NUMBER/DESCRIPTION AM29LV640DU/DH/DL, Am29LV641DH/DL 64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO Control 3.0 Volt-only Read, Program, and Erase Valid Combinations for TSOP and SSOP Packages AM29LV640DH90R, AM29LV640DL90R AM29LV640DH101R, AM29LV640DL101R AM29LV641DH90R, AM29LV641DL90R AM29LV641DH101R, AM29LV641DL101R AM29LV640DH120R, AM29LV640DL120R AM29LV640DH121R, AM29LV640DL121R AM29LV641DH120R, AM29LV641DL120R AM29LV641DH121R, AM29LV641DL121R
Valid Combinations for BGA Packages
Speed/VIO Range 90ns, VIO = 3.0 V - 5.0 V 100 ns, VIO = 1.8 V - 2.9 V 90 ns VIO = 3.0 V - 5.0 V 100 ns VIO = 1.8 V - 2.9 V 120 ns, VIO = 3.0 V - 5.0 V 120 ns, VIO = 1.8 V - 2.9 V 120 ns, VIO = 3.0 V - 5.0 V 120 ns VIO = 1.8 V - 2.9 V AM29LV640DU121R
Order Number
AM29LV640DU90R AM29LV640DU101R PCI WHI
Package Marking
L640DU90N L640DU90R L640DU01N I
Speed/ VIO Range
90 ns, VIO = 3.0 V - 5.0 V 100 ns, VIO = 1.8 V - 2.9 V 120 ns, VIO = 3.0 V - 5.0 V I, E 120 ns, VIO = 1.8 V - 2.9 V
ZI
PCI
PCI, PCE
WHI L640DU01R
L640DU12N
EI, FI
AM29LV640DU120R
WHI, L640DU12R WHE PCI, PCE L640DU21N
ZI, ZE
WHI, L640DU21R WHE
EI, FI, EE, FE
Note: LV640DU has RY/BY#, but no WP#.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Note: LV640/641DH & DL have WP#, but no RY/BY#. U designator in base part number replaced by H or L.
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DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1.
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Sector Group Protect (Note 2) Sector Group Unprotect (Note 2) Temporary Sector Group Unprotect CE# L L L VCC 0.3 V L X L L X OE# L H H X H X H H X WE# H L L X H X L L X
register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Device Bus Operations
RESET# H H H VCC 0.3 V H L VID VID VID WP# ACC Addresses (Note 2) AIN AIN AIN X X X SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L AIN DQ0- DQ15 DOUT (Note 4) (Note 4) High-Z High-Z High-Z (Note 4) (Note 4) (Note 4)
X (Note 3) (Note 3) X X X H H H
X X VHH H X X X X X
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5-12.5 V, VHH = 11.5-12.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0. Sector addresses are A21:A15. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Unprotection" section. 3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in "Sector Group Protection and Unprotection". All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
VersatileIO (VIO) Control
The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on V IO . V IO is available in two configurations (1.8-2.9 V and 3.0-5.0 V) for operation in various system environments. For example, a VI/O of 4.5-5.0 volts allows for I/O at the 5 volt level, driving and receiving signals to and from other 5 V devices on the same data bus.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid
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data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Requirements for Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data.
lect Command Sequence sections for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput during system production. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose-
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater.
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The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is comTable 2.
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
pleted within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Sector Address Table
A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16-bit Address Range (in hexadecimal) 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF
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Table 2.
Sector SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Sector Address Table (Continued)
A18 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 A17 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 A16 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 16-bit Address Range (in hexadecimal) 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF
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Table 2.
Sector SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 A21 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sector Address Table (Continued)
A18 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16-bit Address Range (in hexadecimal) 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF 200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF 268000-26FFFF 270000-277FFF 278000-27FFFF 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF 2F8000-2FFFFF
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Table 2.
Sector SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Sector Address Table (Continued)
A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 16-bit Address Range (in hexadecimal) 300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF
Note: All sectors are 32 Kwords in size.
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Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (8.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 2). Table 3 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 10. This method does not require V ID . Refer to the Autoselect Command Sequence section for more information.
Table 3.
Autoselect Codes, (High Voltage Method)
A21 to A15 X X SA A14 to A10 X X X A8 to A7 X X X A5 to A2 X X X
Description Manufacturer ID: AMD Device ID: LV640DU/H/L, LV641DH/L Sector Protection Verification SecSi Sector Indicator Bit (DQ7), WP# protects highest address sector (LV640DH/641DH), or no WP# (LV640DU) SecSi Sector Indicator Bit (DQ7), WP# protects lowest address sector (LV640DL/641DL)
CE# OE# WE# L L L L L L H H H
A9 VID VID VID
A6 L L L
A1 L L H
A0 L H L
DQ15 to DQ0 0001h 22D7h XX01h (protected), XX00h (unprotected)
L
L
H
X
X
VID
X
L
X
H
H
XX98h (factory locked), XX18h (not factory locked)
L
L
H
X
X
VID
X
L
X
H
H
XX88h (factory locked), XX08h (not factory locked)
Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
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Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4). The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 22 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector groups must first be protected prior to the first sector group unprotect write cycle. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Autoselect Mode section for details.
Table 4.
Sector Group Protection/Unprotection Address Table
A21-A17 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Sector Group SA0-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 SA64-SA67 SA68-SA71 SA72-SA75 SA76-SA79 SA80-SA83 SA84-SA87 SA88-SA91 SA92-SA95 SA96-SA99 SA100-SA103 SA104-SA107 SA108-SA111 SA112-SA115 SA116-SA119 SA120-SA123 SA124-SA127
Note: All sector groups are 128 Kwords in size.
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Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the first or last sector without using VID. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the first or last sector independently of whether those sectors were protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that if WP# is at V IL when the device is in the standby mode, the maximum input load current is increased. See the table in "DC Characteristics". If the system asserts VIH on the WP# pin, the device reverts to whether the first or last sector was previously set to be protected or unprotected using the method described in "Sector Group Protection and Unprotection".
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Group Unprotect Completed (Note 2)
Temporary Sector Group Unprotect
(Note: In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same time (see Table 4)). Notes: 1. All protected sector groups unprotected (If WP# = VIL, the first or last sector will remain protected). 2. All previously protected sector groups are protected once again.
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID (8.5 V - 12.5 V). During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once VID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature.
Figure 1. Temporary Sector Group Unprotect Operation
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START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sector groups: The indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Group Unprotect Mode
No
First Write Cycle = 60h?
First Write Cycle = 60h?
No
Temporary Sector Group Unprotect Mode
Yes Set up sector group address No
Yes All sector groups protected? Yes Set up first sector group address Sector Group Unprotect: Write 60h to sector group address with A6 = 1, A1 = 1, A0 = 0 Reset PLSCNT = 1 Wait 15 ms
Sector Group Protect: Write 60h to sector group address with A6 = 0, A1 = 1, A0 = 0
Wait 150 s
Increment PLSCNT
Verify Sector Group Protect: Write 40h to sector group address twith A6 = 0, A1 = 1, A0 = 0
Read from sector group address with A6 = 0, A1 = 1, A0 = 0 No No PLSCNT = 25? Data = 01h?
Increment PLSCNT
Verify Sector Group Unprotect: Write 40h to sector group address with A6 = 1, A1 = 1, A0 = 0
Yes Yes Protect another sector group? No Remove VID from RESET# Yes
Read from sector group address with A6 = 1, A1 = 1, A0 = 0 No Set up next sector group address Data = 00h?
No
PLSCNT = 1000? Yes
Device failed
Yes
Device failed Write reset command
Last sector group verified? Yes Remove VID from RESET#
No
Sector Group Protect Algorithm
Sector Group Protect complete
Sector Group Unprotect Algorithm
Write reset command
Sector Group Unprotect complete
Figure 2.
In-System Sector Group Protect/Unprotect Algorithms
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SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factor y locked o r custom er locka ble . Th e factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a "1." The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize that sector in any manner they choose. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The SecSi sector address space in this device is allocated as follows: Table 5.
SecSi Sector Address Range 000000h-000007h 000008h-00007Fh
vices are then shipped from AMD's factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD's ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the device may be ordered such that the customer may prog r am a nd p r ot ec t th e 1 2 8- w o rd Se cS i se cto r. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: s Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. s Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the "Sector Group Protection and Unprotection" section. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array.
SecSi Sector Contents
Customer Lockable
Standard ExpressFlash Factory Locked Factory Locked ESN Unavailable ESN or determined by customer Determined by customer
Determined by customer
The system accesses the SecSi Sector through a command sequence (see "Enter SecSi Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. A factory locked device has an 8-word random ESN at addresses 000000h-000007h. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The de-
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 10 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO.
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Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 6-9. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 6-9. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.am d.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.
Table 6.
Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 7.
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 8.
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0017h 0001h 0000h 0000h 0000h 0001h 007Fh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size = 2 byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
N
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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Table 9.
Addresses (x16) 40h 41h 42h 43h 44h Data 0050h 0052h 0049h 0031h 0033h
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 00b = Required, 01b = Not Required Silicon Revision Number (Bits 7-2) 000000b = 0.23 m Process Technology
45h
0000h
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
0002h 0004h 0001h 0004h 0000h 0000h 0000h 00B5h
Erase Suspend 00 = Not Supported, 01 = To Read Only, 02 = To Read & Write Sector Protect 00 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, XX = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum Bits 7-4 = Hex Value in Volts, Bits 0-3 = BCD Value in 100 mV ACC (Acceleration) Supply Maximum Bits 7-4 = Hex Value in Volts, Bits 0-3 = BCD Value in 100 mV Top/Bottom Boot Sector Flag
4Eh
00C5h
4Fh
000Xh
00h = Uniform Sector, No WP# Control 04h = Uniform Sector, WP# Protects Bottom Sector 05h = Uniform Sector, WP# Protects Top Sector
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. September 20, 2002
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AM29LV640D/Am29LV641D
The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram.
The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: s A read cycle at address XX00h returns the manufacturer code. s A read cycle at address XX01h returns the device code. s A read cycle to an address containing a sector group address (SA), and the address 02h on A7-A0 returns 01h if the sector group is protected, or 00h if it is unprotected. (Refer to Table 4 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Table 10 shows the address and data requirements for both command sequences. See also "SecSi (Secured Silicon) Sector Flash Memory Region" for further information.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing.
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hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 10 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. Figure 3 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters, and Figure 15 for timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 10 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence.
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When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY#. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 10 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e ct o r E ra se o r E ra s e S u sp en d d u r in g th e time-out period resets the device to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation.
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Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 10 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 4.
Erase Operation
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Command Definitions
Table 10.
Cycles Command Sequence Read (Note 5) Reset (Note 6) Autoselect (Note 7) Manufacturer ID Device ID SecSi Sector Factory Protect (Note 8) Sector Group Protect Verify (Note 9) First Addr RA XXX 555 555 555 555 555 555 555 555 XXX XXX 555 555 BA BA 55 Data RD F0 AA AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21-A15 uniquely select any sector. 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA PA XXX 2AA 2AA 55 55 55 55 55 55 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 555 555 555 555 555 555 555 555 90 90 90 90 88 90 A0 20 XXX PA 00 PD X00 X01 X03 (SA)X02 0001 22D7 (see Note 8) XX00/ XX01
Command Definitions
Bus Cycles (Notes 1-4) Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Second Addr Data
1 1 4 4 4 4 3 4 4
Enter SecSi Sector Region Exit SecSi Sector Region Program Unlock Bypass Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) CFI Query (Note 14)
3 2 2
6 6 1 1 1
Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. 4. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. During unlock cycles, (when lower address bits are 555 or 2AAh as shown in table) address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status information). The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information.
8.
If WP# protects the highest address sector (or if WP# is not available), the data is 98h for factory locked and 18h for not factory locked. If WP# protects the lowest address sector, the data is 88h for factory locked and 08h for not factor locked. The data is 00h for an unprotected sector group and 01h for a protected sector group.
9.
5. 6.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode.
14. Command is valid when device is ready to read array data or when device is in autoselect mode.
7.
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WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 11 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. invalid. Valid data on DQ0-DQ7 will appear on successive read cycles. Table 11 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 18 in the AC Characteristics section shows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still
START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
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RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. Table 11 shows the outputs for RY/BY#.
Table 11 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 19 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
START
Read DQ7-DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
No
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
Figure 6.
Toggle Bit Algorithm
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DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6 in graphical form.
the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor
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Table 11.
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# (Note 3) 0 0 1 1 0
Standard Mode Erase Suspend Mode
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. RY/BY# is only available on the FBGA package.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +5.5 V A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .-0.5 V to +12.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 7. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is -0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns
Figure 7. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . -55C to +125C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0-3.6 V VIO . . . . . . . . . . . . . . . . .either 1.8-2.9 V or 3.0-5.0 V (see Ordering Information section)
Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILO ICC1 ICC2 ICC3 ICC4 ICC5 IACC VIL VIH VHH VID VOL VOH1 VOH2 VLKO Low VCC Lock-Out Voltage (Note 7) Parameter Description Input Load Current (Note 1) A9, ACC Input Load Current Output Leakage Current VCC Active Read Current (Notes 2, 3) Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max 5 MHz CE# = VIL, OE# = VIH 1 MHz 9 2 26 0.2 0.2 0.2 5 15 -0.5 0.7 x VCC VCC = 3.0 V 10% VCC = 3.0 V 10% IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 0.8 VIO VIO-0.4 2.3 2.5 11.5 8.5 Min Typ Max 1.0 35 1.0 16 4 30 5 5 5 10 30 0.8 VCC + 0.3 12.5 12.5 0.45 mA mA A A A mA mA V V V V V V V V Unit A A A
VCC Active Write Current (Notes 3, 4) CE# = VIL, OE# = VIH, WE# = VIL VCC Standby Current (Note 3) VCC Reset Current (Note 3) Automatic Sleep Mode (Notes 3, 5) ACC Accelerated Program Current Input Low Voltage (Note 6) Input High Voltage (Note 6) Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage CE#, RESET# = VCC 0.3 V, WP# = VIH RESET# = VSS 0.3 V, WP# = VIH VIH = VCC 0.3 V; VIL = VSS 0.3 V, WP# = VIH ACC pin CE# = VIL, OE# = VIH VCC pin
Notes: 1. On the WP# pin only, the maximum input load current when WP# = VIL is 5.0 A. 2. 3. 4. 5. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V 7. Not 100% tested.
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DC CHARACTERISTICS Zero-Power Flash
25 Supply Current in mA
20
15
10
5 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000
Note: Addresses are switching at 1 MHz
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
3.6 V
10
8 Supply Current in mA
3.0 V
6
4
2
0 1
Note: T = 25 C
2
3 Frequency in MHz Figure 10. Typical ICC1 vs. Frequency
4
5
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AM29LV640D/Am29LV641D
September 20, 2002
TEST CONDITIONS
Table 12.
3.3 V Test Condition Device Under Test CL 6.2 k 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Note: Diodes are IN3064 or equivalent 30 5 0.0-3.0 1.5 0.5 VIO
Test Specifications
90R, 101R 120R, 121R 1 TTL gate 100 pF ns V V V Unit
Figure 11.
Test Setup
Output timing measurement reference levels
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
3.0 V 0.0 V
Input
1.5 V
Measurement Level
0.5 VIO V
Output
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and Measurement Levels
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AC CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tRC tACC tCE tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Read Output Enable Hold Toggle and Time (Note 1) Data# Polling CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Options 90R 90 90 90 35 30 30 101R 100 100 100 35 30 30 0 0 10 120R, 121R 120 120 120 50 30 30 Unit ns ns ns ns ns ns ns ns ns
tOEH
Notes: 1. Not 100% tested. 2. See Figure 11 and Table 12 for test specifications.
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 13.
Read Operation Timings
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AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 14.
Reset Timings
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AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tWHWH1 tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH1 tWHWH2 tVHH tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Word Programming Operation (Note 2) Accelerated Word Programming Operation (Note 2) Sector Erase Operation (Note 2) VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min Min 35 45 45 Speed Options 90R 90 101R 100 0 15 45 0 45 0 20 0 0 0 35 30 11 7 0.9 250 50 0 90 50 50 50 120R, 121R 120 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s sec ns s ns ns
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AM29LV640D/Am29LV641D
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AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
otes: . PA = program address, PD = program data, DOUT is the true data at the program address. . Illustration shows device in word mode.
Figure 15.
Program Operation Timings
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 16.
Accelerated Program Timing Diagram
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AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase In Progress Complete
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status". 2. These waveforms are for the word mode.
Figure 17.
Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 18. Data# Polling Timings (During Embedded Algorithms)
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AC CHARACTERISTICS
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 20.
DQ2 vs. DQ6
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AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP tRRB Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Group Unprotect Min Min Min All Speed Options 500 4 4 Unit ns s s
Note: Not 100% tested.
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID VSS, VIL, or VIH
WE# tRSP RY/BY# tRRB
Figure 21.
Temporary Sector Group Unprotect Timing Diagram
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AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect or Unprotect
Valid* Verify 40h
Sector Group Protect: 150 s, Sector Group Unprotect: 15 ms
Valid*
Data
60h
60h
Status
1 s CE#
WE#
OE#
For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22.
Sector Group Protect and Unprotect Timing Diagram
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Word Programming Operation (Note 2) Accelerated Word Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 45 45 45 Speed Options 90R 90 101R 100 0 45 45 0 0 0 0 45 30 11 7 0.9 50 50 50 120R, 121R 120 Unit ns ns ns ns ns ns ns ns ns ns s s sec
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
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AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 23.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
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ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Typ (Note 1) 0.9 115 11 7 48 300 210 144 Max (Note 2) 15 Unit sec sec s s sec Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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AM29LV640D/Am29LV641D
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PHYSICAL DIMENSIONS SSO056--56-Pin Shrink Small Outline Package (SSOP)
Dwg rev AB; 10/99
50
AM29LV640D/Am29LV641D
September 20, 2002
PHYSICAL DIMENSIONS FBE063--63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package
Dwg rev AF; 10/99
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PHYSICAL DIMENSIONS LAA064--64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm package
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AM29LV640D/Am29LV641D
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PHYSICAL DIMENSIONS TS 048--48-Pin Standard TSOP
Dwg rev AA; 10/99
Note: For reference only. BSC is an ANSI standard for Basic Space Centering.
September 20, 2002
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PHYSICAL DIMENSIONS TSR048--48-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
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AM29LV640D/Am29LV641D
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REVISION SUMMARY Revision A (April 26, 1999)
Initial release. Ordering Information Added the valid combinations for the SSOP package.
Revision A+1 (May 4, 1999)
Global Deleted references to the 4-word unique ESN. Replaced references to VCCQ with VIO. Connection Diagrams 63-ball FBGA: Corrected signal for ball H7 to VIO. Ordering Information Added "U" designator description. SecSi (Secured Silicon) Sector Flash Memory Region In the third paragraph, replaced references to boot sectors with SA0. Added table to show SecSi sector contents. DC Characteristics table Added VIO = VCC as a test condition for ICC1 and ICC2. Changed V HH minimum specification from 8.5 V to 11.5 V.
Revision A+6 (September 28, 1999)
Connection Diagrams Clarified which packages are available for a particular part number. Device Bus Operations VersatileIO Control: Added comment to contact AMD for more information on this feature. DC Characteristics CMOS Compatible table: Added notes (1 and 2) for ILI and test conditions column. Test Conditions In Test Specifications table and Input Waveforms and Meaurement Levels figure, changed the output measurement level to VIO/2. AC Characteristics Read-only Operations table: Added note for test setup column.
Revision A+2 (May 14, 1999)
Ordering Information Clarified the differences between the H, L, and U designators.
Revision B (June 20, 2000)
Global Deleted references to 150 ns speed option. Added more information and specifications on VIO feature, including part number distinctions. At V IO < V CC , the available speed options are 100 ns and 120 ns. At VIO VCC, the available speed options are 90 ns and 120 ns. Changed data sheet status to "Preliminary." Distinctive Characteristics Clarified on which devices RY/BY# and WP# are available. Clarified package options for devices. Ordering Information Clarified on which devices RY/BY# and WP# are available. Clarified package options for devices. Reinstated "0" into the 120 ns speed part number for VIO = 3.0 V to 5.0 V; added part numbers for VIO = 1.8 V to 2.9 V. Device Bus Operations table In the legend, corrected the VHH voltage range. SecSi Sector Contents table Corrected ending address in second row to 7Fh. DC Characteristics table Redefined VOH1 and VOH2 in terms of VIO. Added note relative to VIO for VIH and VIL. Deleted note regarding test condition assumption of VIO = VCC.
Revision A+3 (June 7, 1999)
Product Selector Guide Added note under table. Ordering Information Deleted the "0" from the 120 and 150 ns part numbers. Corrected the FBGA package marking for the 150 ns speed option.
Revision A+4 (June 25, 1999)
Global Information on the 56-pin SSOP package has been added: pinout information and physical dimension drawings. Command Definitions Corrected the data for SecSi Sector protection in Note 9. Added device ID data to the table.
Revision A+5 (August 2, 1999)
Block Diagram Separated WP# and ACC.
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AM29LV640D/Am29LV641D
55
Test Conditions Test Conditions table: Redefined output timing measurement reference level as 0.5 VIO. Added note to table and figure. Erase and Program Opeations table, Alternate CE# Controlled Erase and Program Operations table, Erase and Programming Performance table Changed the typical sector erase time to 1.6 s. AC Characteristics--Figure 15. Program Operations Timing and Figure 17. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations.
where VIO VCC, and 100 and 120 ns speeds are available where VIO < VCC.
Revision B+4 (March 8, 2001)
Table 4, Sector Group Protection/Unprotection Address Table Corrected the sector group address bits for sectors 64-127.
Revision B+5 (October 11, 2001)
Connection Diagrams, Ordering Information, Physical Dimensions Added 64-ball Fortified BGA package information.
Revision B+6 (January 10, 2002)
Global Clarified description of VersatileIO (VIO) in the following sections: Distinctive Characteristics; General Description; VersatileIO (VIO) Control; Operating Ranges; DC Characteristics; CMOS compatible. Reduced typical sector erase time from 1.6 s to 0.9 s. DC Characteristics Changed minimum VOH1 from 0.85VIO to 0.8VIO . Deleted reference to Note 6 for both VOH1 and VOH2. Erase and Program Performance table Reduced typical sector erase time from 1.6 s to 0.9 s. Changed typical chip program time from 90 s to 115 s.
Revision B+1 (August 4, 2000)
Global Added trademarks for SecSi Sector. Accelerated Program Operation (page 12), Unlock Bypass Command Sequence (page 26) Added caution note regarding ACC pin. Absolute Maximum Ratings Corrected the maximum voltage on VIO to +5.5V. DC Characteristics table Added WP# = VIH to test conditions for standby currents ICC3, ICC4, ICC5.
Revision B+7 (April 15, 2002)
Ordering Information Added N designator for Fortified BGA package markings. Common Flash Interface (CFI) Revised data value at address 44h. Clarified description of data for addresses 45-47h, 49, 4A, 4D-4Fh. Table 10, Command Definitions Clarified and combined Notes 4 and 5 into Note 4.
Revision B+2 (October 18, 2000)
Distinctive Characteristics Corrected package options for 56-pin SSOP as being available on AM29LV640DH/DL only.
Revision B+3 (January 18, 2001)
Global Deleted "Preliminary" status from document. General Description In the second paragraph, corrected references to VIO voltage ranges. The 90 and 120 speeds are available
Revision B+8 (September 20, 2002)
Sector Erase Command Sequence Changed sentence arrangement in fourth paragraph.
Trademarks Copyright (c) 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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